Exploring the Distinct Hysteresis Behavior and Suppression Strategy in Tellurium FETs

Sung-Tsun Wang^1,2*, Der-Hsien Lien¹

¹Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan
²Institute of Pioneer Semiconductor Innovation, National Yang Ming Chiao Tung University, Hsinchu, Taiwan

* Presenter:Sung-Tsun Wang, email:beckham880415@gmail.com

Tellurium (Te), composed of one-dimensional helical chains in a hexagonal structure, offers high hole mobility and strong potential for spintronic, transistor, and optoelectronic applications. However, pronounced electrical hysteresis limits its device stability. In this study, electrical characterization of Te transistors reveals that hysteresis enlarges with the gate sweep range and persists even under solely positive or negative bias, indicating it is not caused by a single trap type. When measured under 10⁻⁵ Torr, the hysteresis decreases by ~56%, suggesting that ambient gas molecules play a major role. The mechanism is attributed to dipolar species such as water vapor, whose polarization responds to carrier modulation in the Te channel. By encapsulating Te with Al₂O₃ on both sides, nearly hysteresis-free transfer curves are achieved, with an Iₒₙ/Iₒff ratio >10⁴ and mobility exceeding 80 cm² V⁻¹ s⁻¹.

Keywords: Tellurium, p-type, FET, Electrical hysteresis, TFT