High-k vdW Dielectric for 2D FETs Toward BEOL via Direct Deposition

You-Jia Huang^1*, Hui-Chun Huang², Bor-Wei Liang³, Hung-Wei Yen⁴, Min-Hung Lee⁵, Ching-Yuan Su⁶, Yann-Wen Lan¹

¹Department of physics, National Taiwan Normal University, Taipei 116, Taiwan
²Department of Materials and Optoelectronic Science, National Sun Yat-Sen University, Kaohsiung 80424, Taiwan
³Institute of Electro-Optical Science and Technology, National Taiwan Normal University, Taipei 116, Taiwan
⁴International Graduate Program of Molecular Science and Technology, National Taiwan University, Taipei 116, Taiwan
⁵Graduate School of Advanced Technology, National Taiwan University, Taipei 116, Taiwan
⁶Department of Mechanical Engineering, National Central University, Taoyuan 320, Taiwan

* Presenter:You-Jia Huang, email:61341001S@gapps.ntnu.edu.tw

Two-dimensional FET holds great potential but faces significant challenges for combining Si-based devices in the back-end of line 3DICs. One of the reasons that induces carrier scattering in 2D channel is the fabrication process of top-gate dielectrics and the presence of dangling bonds. This study emphasizes the physical property and enhances the dielectric performance of physical vapor deposition Sb₂O₃, a high-k Ven der Waal oxide, to demonstrate a top-gate MoS₂ MOSFET. Under 5.2 nm EOT and band structure design, the device achieves 10⁶ on/off current ratio, and low interface trap density with 2×10¹¹ (1/cm²eV¹). A 2T0C structure DRAM that exhibits program retention under a 10-ms pulse operation by two transistors integration. Applying inorganic oxide as a high-k dielectric and the demonstration 2T0C layout are strong candidates for next-generation applications in manufacturing technologies.

Keywords: high-k material, 2D FET, vdW dielectric, DRAM